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1/16 september 2001 n high speed : f max = 38mhz (typ.) at v cc = 6v n low power dissipation: i cc =4 m a(max.) at t a =25c n high noise immunity: v nih = v nil = 28 % v cc (min.) n symmetrical output impedance: |i oh | = i ol = 4ma (min) n balanced propagation delays: t plh @ t phl n wide operating voltage range: v cc (opr) = 2v to 6v n pin and function compatible with 74 series 40103 description the m74hc40103 is an high speed cmos 8-stage presettable synchronous down counter fabricated with silicon gate c 2 mos technology. the hc40103 consists of an 8 stage synchronous down counter with a single output which is active when the internal count is zero. the hc40103 contains a single 8-bit binary counter. this device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. all control inputs and the carry-out / zero detect output are active low logic. in normal operation the counter is decremented by one count on each positive transition of the clock. counting is inhibited when the carry-in / counter enable (ci/ce ) input is high. the carry-out / zero-detect (co/zd ) output goes low when the count reaches zero if the ci/ce input is low, and remains low for one full clock period. when the synchronous preset-enable (spe) input is low, data at the j input is clocked into the counter on the next positive clock transition regardless of the state of the ci/ce input. when the asynchronous preset-enable (ape) input is low, data at the j inputs is asynchronously forced into the counter regardless of the state of the spe ci/ce or clock inputs. j input j0-j7 represent a singular 8-bit binary word. when the clear, clr input is low, the counter is asynchronously cleared to its maximum count m74hc40103 8 stage presettable synchronous down counter pin connection and iec logic symbols order codes packag e tube t & r dip m74hc40103b1r sop m74hc40103m1r m74hc40103rm13tr tssop M74HC40103TTR tssop dip sop
m74hc40103 2/16 (255 10 ) regardless of the state of any other input. the precedence relationship between control input is indicated in the truth table. if all control inputs are high at the time of zero count, the counters will jump to the maximum count giving a input and output equivalent circuit counting sequence of 256 clock pulses long. the hc40103 may be cascaded using the ci/ce input and the co/zd output, in either a synchronous or ripple mode. all inputs are equipped with protection circuits against static discharge and transient excess voltage. pin description truth table x : dont care maximum count is "255" pin no symbol name and function 1 clock clock input (low to high edge triggered) 2 clear asynchronous master reset input (active low) 3 ci/ce terminal enable input 4, 5, 6, 7, 10, 11, 12, 13 j0 to j9 jam inputs 9ape asynchronous preset enable inputs(active low) 14 co/zd terminal count output (active low) 15 spe synchronous preset enable input (active low) 8 gnd ground (0v) 16 vcc positive supply voltage control inputs mode functional description clear ape spe ci/ce h h h h count inhibit even if clock is given, no count is made h h h l regular count down count at rising edge of clock hh l x synchronous preset data of pi terminal is preset at rising edge of clock hlxx asynchronous preset data of pi terminal is asynchronously preset to clock l x x x clear counter is set to maximum count
m74hc40103 3/16 logic diagram timing chart
m74hc40103 4/16 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 c to 85 c recommended operating conditions symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2 to 6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r , t f input rise and fall time v cc = 2.0v 0 to 1000 ns v cc = 4.5v 0 to 500 ns v cc = 6.0v 0 to 400 ns
m74hc40103 5/16 dc specifications ac electrical characteristics (c l = 50 pf, input t r = t f = 6ns) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il low level input voltage 2.0 0.5 0.5 0.5 v 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh high level output voltage 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-4.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-5.2 ma 5.68 5.8 5.63 5.60 v ol low level output voltage 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =4.0 ma 0.17 0.26 0.33 0.40 6.0 i o =5.2 ma 0.18 0.26 0.33 0.40 i i input leakage current 6.0 v i = v cc or gnd 0.1 1 1 m a i cc quiescent supply current 6.0 v i = v cc or gnd 44080 m a symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t tlh t thl output transition time 2.0 30 75 95 110 ns 4.5 8151922 6.0 7131619 t plh t phl propagation delay time (ck - co/zd ) 2.0 96 185 230 280 ns 4.5 24 37 46 56 6.0 20 31 39 47 t plh t phl propagation delay time (ape - co/zd ) 2.0 116 225 280 340 ns 4.5 29 45 56 68 6.0 25 38 48 57 t plh t phl propagation delay time (cl - co/zd ) 2.0 104 200 250 300 ns 4.5 26 40 50 60 6.0 22 34 43 51 t plh t phl propagation delay time (ci/ce - co/zd ) 2.0 48 95 120 145 ns 4.5 12 19 24 29 6.0 10 16 20 24
m74hc40103 6/16 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc f max maximum clock frequency 2.0 4 8 3 2.6 mhz 4.5 20 32 16 13 6.0 24 38 19 15 t w clock pulse width high or low 2.0 150 20 195 235 ns 4.5 30 7 36 45 6.0 25 5 32 40 t w clear pulse width low 2.0 115 35 140 175 ns 4.5 20 12 28 35 6.0 19 10 24 30 t w preset enable pulse width ape , low 2.0 115 31 140 175 ns 4.5 20 11 28 35 6.0 19 9 24 30 t rem removal time clear to clock or ape to clock 2.0 47 12 62 70 ns 4.5 9 4 12 13 6.0 8 3 10 11 t setup set up time spe to clock 2.0 70 20 90 110 ns 4.5 13 7 16 20 6.0 11 5 15 16 t setup set up time ci/ce to clock 2.0 140 40 175 205 ns 4.5 27 14 36 42 6.0 23 12 31 36 t setup set up time jn to clock 2.0 72 20 92 105 ns 4.5 14 8 18 20 6.0 12 6 15 18 t hold hold time spe to clock 2.0 -14 0 0 0 ns 4.5 -5 0 0 0 6.0 -4 0 0 0 t hold hold time ci/ce to clock 2.0 -30 0 0 0 ns 4.5 -11 0 0 0 6.0 -9 0 0 0 t hold hold time jn to clock 2.0 -17 0 0 0 ns 4.5 -6 0 0 0 6.0 -5 0 0 0 symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5.0 5101010pf c pd power dissipation capacitance (note 1) 5.0 60 pf symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max.
m74hc40103 7/16 functional description this device is an 8-stage presettable synchronous down counter. carry out/zero detect (co/zd ) is output at the "l" level for the period of 1 bit when the readout becomes "0". this device adopts 8-bit-binary counter decimal notation, making setting up to 255 counts possible. count operation at the "h" level of control input of clear , spe and ape , the counter carriers out down count operation one by one at the rise of pulse given to clock input. count operation can be inhibited by setting carry input/clock enable ci/ce to the "h" level. co/zd is output at the "l" level when the readout becomes "0" but is not output even if the readout becomes "0" when ci/ce is at the "h" level, thus maintaining the "h" level. synchronous cascade operation can be carried out by using ci/ce input and co/zd output. the contents of count jump to maximum count (255) if clock is given when the readout is "0". therefore, operation of 256-frequency division is carried out when clock input alone is given without various kinds of preset operation. preset and reset operation when clear (clear ) input is set to the "l" level, the readout is set to the maximum count independently of other inputs. when asynchronous preset enable (ape ) input is set to the "l" level, readouts given on j0 to j7 can be preset asynchronously to the counter independently of inputs other than clear input. when synchronous preset enable (spe ) is set to the "l" level the readouts given on j0 to j7 can be preset to counter synchronously with the rise of clock. as to these operation mode, refer to the truth table. inputs output clear ape spe jte clock q n + 1 lxxxx x l hlxlx x l hlxhx x h hhl l x l hhlhx h hhl xx q n hhhx l qn hhhxh x q n
m74hc40103 8/16 typical applications programmable divide-by-n counter parallel carry cascading programmable timer f out = f in / (n+1) timing chart when n = "3" (j0, j1 = v cc , j2-j7 = gnd hc40103 ... 1/2 to 1/256 are dividable * at synchronous cascade connection, huzzerd occurs at c0 output after its second stage when digit place changes, due to delay arrival. therefore, take gate from hc32 or the like, not from c0 output at the rear stage directly the above formula does not take into account the phase of clock input. therefore, the real pulse width is the distance between the above formula-1/f in ~ the above formula
m74hc40103 9/16 test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r t = z out of pulse generator (typically 50 w ) waveform 1 : propagation delay time (f=1mhz; 50% duty cycle)
m74hc40103 10/16 waveform 2 : propagation delay, minimum pulse width and removal time (f=1mhz; 50% duty cycle) waveform 3 : propagation delay, minimum pulse width and removal time (f=1mhz; 50% duty cycle)
m74hc40103 11/16 waveform 4 : propagation delay time (f=1mhz; 50% duty cycle) waveform 5 : minimum setup time (f=1mhz; 50% duty cycle)
m74hc40103 12/16 waveform 6 : minimum setup time (f=1mhz; 50% duty cycle)
m74hc40103 13/16 dim. mm. inch min. typ max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 plastic dip-16 (0.25) mechanical data p001c
m74hc40103 14/16 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
m74hc40103 15/16 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
m74hc40103 16/16 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com

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